1. Field of the Invention
This invention generally relates to a semiconductor logic device, and, in particular, to a programmable logic device including AND plane and an OR plane, at least one of which is programmable and which may be partially enabled or disabled selectively.
2. Description of the Prior Art
A programmable logic device is well known in the art, and it typically includes an AND gate array (AND plane) and an OR gate array (OR plane), at least one of which is programmable by the user. In one form, a programmable logic device (PLD) includes an AND plane and an OR plane, both of which are programmable by the user. In another form, a programmable logic device includes a programmable AND plane and a fixed and thus non-programmable OR plane. This latter form of PLD is also called a programmable array logic or PAL.
In either form of PLD, an AND plane includes a plurality of input lines extending in a first direction in parallel and a plurality of product term lines extending in a second direction, which is different from the first direction, in parallel. And, a programmable element, such as a programmable memory transistor, is provided at each intersection between the input and product term lines. For example, in the case of a programmable logic device having a fixed OR plane, the number of product term lines to be connected to one OR gate is previously determined for each product and it cannot be changed by the user.
In a PLD, it is rather rare to use all of the product term lines and some of the product term lines are usually left unused depending on the kind of a logic desired to be programmed by the user. However, in the prior art PLD, irrespective of whether all of the product term lines are used or not, all of the product term lines are kept enabled or in an operative state. This is disadvantageous because additional power is consumed by these product term lines which are not used. For example, if there are sixteen product term lines connected to a single OR gate and only four of them are used, three quarters of the total power consumed by the product term lines connected to this OR gate are wasted. In general, the use rate of the product term lines in a PLD having a fixed OR plane is in a range from 30 to 40% on the average. It is thus clear that a significant amount of power is wasted in the prior art PLD.